At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC […]
This paper explains the Calibre Auto-Waiver product, and discusses how the auto-waiver process significantly reduces the time and risks associated with implementing third-party IP. Integration of third-party intellectual property (IP) into integrated circuit (IC) designs has always been a potential time trap for IC designers. IP design rule violations that were waived by the foundry […]
Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP […]
Thirty five years have passed since the first lithography process models were presented, and since that time there has been remarkable progress in the predictive power, performance, and applicability of these models in addressing many different challenges within the semiconductor industry. The impact has been profound, and this paper will attempt to highlight some of […]
Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and […]
In 2009 a new European initiative on Double Patterning and Double Exposure lithography process development was started in the framework of the ENIAC Joint Undertaking. The project, named LENS (Lithography Enhancement Towards Nano Scale), involves twelve companies from five different European Countries (Italy, Netherlands, France, Belgium Spain) and includes: IC makers (Numonyx and STMicroelectronics), a […]
Selective Inverse Lithography (ILT) approach recently introduced by authors [1] has proven to be advantageous for extending life-span of lower-NA 193nm exposure tools to achieve satisfactory 65nm contact layer patterning. We intend to find an alternative solution without the need for higher NA tools and advanced light source optimization. In this paper we explore possible […]
Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device […]
By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently chip delivery. To diminish the risk of sensitive layout structures, and avoid or reduce design delays, designers need the […]
In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, […]
