Market demands for increasing functionality in mobile platforms and the explosion in IoT devices have put immense pressure on chip design groups to lower power consumption.
Devices that run on batteries or other standalone energy sources are not alone in requiring power analysis solutions. Engineers developing semiconductors for systems that run off external power –– i.e., though that are plugged in –– also need to understand power consumption accurately, especially consumption under the chip’s realistic operating conditions. For example, these designers need to ensure that their power distribution networks and chip packaging meet the peak-power demands of the circuitry.
If they underestimate the peak power consumption in the device, they likely will under-design the power distribution network. This will result in excessive IR-drop in the power grid. And in a worst case scenario, excessive IR-drop reduces noise margins that can cause a device to fail under high-loading conditions. Other negative effects of excessive IR drop include reduced device reliability and diminished performance (e.g., slower switching speeds).
Conversely, overestimating peak power can lead to over-design of the power grids, resulting in much higher cost due to increases in the chip area and number of metal layers to supply the power and ground planes.
Similar to the power grid, design considerations for the chip packaging have to be considered. Under peak power loads, a significant voltage drop could be due to the inductance at the package pins. This voltage drop (di/dt-drop) results is similar negative affects with respect to noise margins and device performance.
High-performance systems containing advanced microprocessors, graphics and networking chips are particularly vulnerable to these affects.
Peak power after P&R
Until now, the solutions that allow these effects to be analyzed and understood have only become available in the design cycle, usually after place and route. Fixing power distribution problems this late in the design is both costly and time consuming. Care must be taken to ensure the proper conditions are analyzed to understand worst-case scenarios.
Moreover, the speed and capacity of current solutions have greatly limited the size of the design and the length of simulation scenarios for analysis available to the user. Typically, IR drop analysis can only been done for a few vectors (cycles) due to speed and capacity limitations. Without analyzing realistic scenarios under real hardware and software loads, peak-power conditions are easily missed leading to under-design of power distribution and packaging solutions.
Designers require a methodology to find peak-power situations under realistic loads and apply these peak conditions to their IR drop and di/dt-drop analysis. Otherwise, they face a severe risk of failing to meet their design’s speed, reliability and operability goals.
Fortunately, the landscape is starting to change. One promising methodology provides accurate dynamic peak-power analysis and characterization under realistic operating scenarios. Engineers can now confidently assess peak-power issues in their designs and easily correct them to address power distribution and packaging needs. Figure 1 gives some flavor of the way ahead – the challenges we face mean it is sure to attract more than its fair share of followers.