Verilog

May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.

Guide | Topics: EDA - Verification | Tags: assertions, lint, RTL, RTL signoff, SystemVerilog, Verilog, VHDL

October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.

Article | Topics: EDA Topics, EDA - ESL, IC Implementation | Tags: FPGA, ISE Design Suite, Matlab, place and route, programmable logic, Simulink, synthesis, SystemC, SystemVerilog, Verilog, VHDL, Virtex 7, Xilinx | Organizations: Xilinx

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