August 31, 2017
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
July 25, 2017
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
March 15, 2017
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
March 15, 2017
DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。
July 15, 2016
To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
May 29, 2014
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
October 23, 2012
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
May 23, 2012
VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
April 5, 2012
More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
March 28, 2012
Verification IP is becoming an increasingly important component for system design due to the rapid proliferation of new protocols and interfaces, chiefly driven by mobile comms.