A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
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