Clock tree synthesis
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
clock distribution
Enabling FPGA prototyping of large ASIC and SoC designs
How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
PLATINUM SPONSORS
View All Sponsors