20nm

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.

The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies