How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.
Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
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