A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
Learn how planning and upfront knowledge of the challenges ahead can open up what has seemed a challenging task.
Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
A new version of the automotive safety standard arrives later this year. Review the main updates and see how it will combine with the incoming SOTIF autonomous driving standard.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
The article describes a pre-silicon strategy for the design and verification of SSD controllers that is faster and more flexible than ICE using physical NAND on a daughter-card.
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
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