How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
German consultancy E-Cooling describes its strategy for thermal and airflow analysis.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
Seven core considerations will help you realize your PCB for the Internet of Things more effectively.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
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