Mentor has untethered its Veloce platform online because it feels more designs need emulation and the cloud can now support it.
The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Machine learning is gradually moving into implementation and verification tools for EDA.
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